View FIN1026_172973.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FIN1026 3.3V LVDS 2-Bit High Speed Differential Receiver
June 2002 Revised June 2002
FIN1026 3.3V LVDS 2-Bit High Speed Differential Receiver
General Description
This dual receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock and data. The FIN1026 can be paired with its companion driver, the FIN1025, or any other LVDS driver.
Features
s Greater than 400Mbs data rate s Flow-through pinout simplifies PCB layout s 3.3V power supply operation s 0.4ns maximum differential pulse skew s 2.5ns maximum propagation delay s Low power dissipation s Power-Off protection s Fail safe protection for open-circuit, shorted and terminated non-driven input conditions s Meets or exceeds the TIA/EIA-644 LVDS standard s 14-Lead TSSOP package saves space
Ordering Code:
Order Number FIN1026MTC Package Number MTC14 Package Description 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Pin Name ROUT1, ROUT2 RIN1+, RIN2+ RIN1-, RIN2- EN EN VCC GND NC Description LVTTL Data Outputs Non-Inverting LVDS Inputs Inverting LVDS Inputs Driver Enable Pin Inverting Driver Enable Pin Power Supply Ground No Connect
Truth Table
Inputs EN H H H X L or Open EN L or Open L or Open H X RIN+ H L X X RIN- L H X X Outputs ROUT H L H Z Z
L or Open Fail Safe Condition
H = HIGH Logic Level L = LOW Logic Level X = Don't Care Z = High Impedance Fail Safe = Open, Shorted, Terminated
(c) 2002 Fairchild Semiconductor Corporation
DS500784
www.fairchildsemi.com
FIN1026
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) LVDS DC Input Voltage (VIN) LVTTL DC Input Voltage (VIN) DC Output Voltage (VOUT) DC Output Current (IO) Storage Temperature Range (TSTG) Max Junction Temperature (TJ) Lead Temperature (TL) (Soldering, 10 seconds) ESD (Human Body Model) ESD (Machine Model) 260C 10,000V 600V
-0.5V to +4.6V -0.5V to +4.6V -0.5V to 6V -0.5V to 6V
16mA
Recommended Operating Conditions
Supply Voltage (VCC) Magnitude of Differential Voltage (|VID|) Common-Mode Input Voltage (VIC) Input Voltage (VIN) Operating Temperature (TA) 100mV to VCC 0.05V to 2.35V 0 to VCC 3.0V to 3.6V
-65C to +150C
150C
-40C to +85C
Note 1: The "Absolute Maximum Ratings": are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specification.
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol VTH VTL IIN II(OFF) VOH VOL IOZ VIK IOS ICCZ ICC Parameter Differential Input Threshold HIGH Differential Input Threshold LOW Input Current Power-Off Input Current Output HIGH Voltage Output LOW Voltage Disabled Output Leakage Current Input Clamp Voltage Output Short Circuit Current Disabled Power Supply Current Power Supply Current Test Conditions See Figure 1, VIC = +0.05V, +1.2V, or 2.35V See Figure 1, VIC = +0.05V, +1.2V, or 2.35V VIN = 0V or VCC VCC = 0V, VIN = 0V or 3.6V IOH = -100 A IOH = -8 mA IOH = 100 A IOL = 8 mA EN = 0.8 and EN* = 2V, VOUT = 3.6V or 0V IIK = -18 mA Receiver Enabled, VOUT = 0V (one output shorted at a time) Receiver Disabled Receiver Enabled, (RIN+ = 1V and RIN- = 1.4V) or (RIN+ = 1.4V and RIN- = 1V)
Note 2: All typical values are at TA = 25C and with VCC = 3.3V.
Min
Typ (Note 2)
Max 100
Units mV mV A A V
-100 20 20 VCC -0.2 2.4 3.29 3.1 0 0.18 -1.5 -15 2.6 4.8 -0.8 -100 5 8.5 0.2 0.5 20
V A V mA mA mA
www.fairchildsemi.com
2
FIN1026
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol tPLH tPHL tTLH tTHL tSK(P) tSK(LH) tSK(HL) tSK(PP) fMAX tPZH tPZL tPHZ tPLZ CIN COUT Parameter Propagation Delay LOW-to-HIGH Propagation Delay HIGH-to-LOW Output Rise Time (20% to 80%) Output Fall Time (80% to 20%) Pulse Skew |tPLH - tPHL| Channel-to-Channel Skew (Note 4) Part-to-Part Skew (Note 5) Maximum Operating Frequency (Note 6) LVTTL Output Enable Time from Z to HIGH LVTTL Output Enable Time from Z to LOW LVTTL Output Disable Time from HIGH to Z LVTTL Output Disable Time from LOW to Z Input Capacitance Output Capacitance Enable Inputs RIN Inputs
Note 3: All typical values are at TA = 25C and with VCC = 3.3V. Note 4: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction. Note 5: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits. Note 6: fMAX Criteria: Input tR = tF < 1 ns, VID = 300 mV, (1.05V to 1.35V pp), 50% duty cycle; Output duty cycle 40% to 60%, VOL < 0.5V, VOH > 2.4V. All channels switching in phase.
Test Conditions
Min 1.0 1.0
Typ (Note 3)
Max 2.5 2.5
Units ns ns ns ns ns ns ns MHz ns ns ns ns pF pF
0.7 |VID| = 400 mV, CL = 10 pF See Figure 1 and Figure 2 0.7
1.2 1.2 0.4 0.3 1.0
200 RL = 1k, CL = 10 pF, See Figure 3
375 6.0 6.0 6.0 6.0 3.0 4.2 6
Note A: All differential input pulses have frequency = 10MHz, tR or tF = 1ns
FIGURE 1. Differential Receiver Voltage Definitions
3
www.fairchildsemi.com
FIN1026
FIGURE 2. LVDS Input to LVTTL Output AC Waveforms
Test Circuit for LVTTL Outputs
Voltage Waveforms Enable and Disable Times
FIGURE 3. LVTTL Outputs Test Circuit and AC Waveforms
www.fairchildsemi.com
4
FIN1026 3.3V LVDS 2-Bit High Speed Differential Receiver
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
www.fairchildsemi.com

▲Up To Search▲

Price & Availability of FIN1026

	To Download FIN1026 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .